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HD74CDCV851 2.5 v pll clock buffer for ddr application ade-205-653f (z) rev.6 dec. 2002 description the HD74CDCV851 is a high-performance, low-skew, lo w-jitter, pll clock buffer. it is specifically designed for use with ddr (double data rate) system board application. features ? designed for ddr pc mother board clock buffering ? supports 60 mhz to 170 mhz operation range ? distributes one to ten differential clock outputs pairs ? spread spectrum clock compatible ? external feedback pin (fbin) are used to synchronize the outputs to the clock input ? supports 2.5 v analog supply voltage (avdd), and 2.5 v vdd ? 48pin ssop package ? support output enable by i 2 c tm programming ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) HD74CDCV851ssel ssop-48 pin ? ss el (1,000 pcs / reel) note: please consult the sales office for the above package availability. note: i 2 c is a trademark of philips corporation.
HD74CDCV851 rev.6, dec. 2002, page 2 of 16 key specifications ? supply voltages : vdd = avdd = 2.5 v0.2 v ? output clock cycle to cycle jitter = 75 ps ? output clock pin to pin skew = 100 ps max function table inputs outputs *1 avdd clk yn yn fbout pll gnd l l h l bypass / off gnd h h l h bypass / off 2.5 v (typ.) l l h l running 2.5 v (typ.) h h l h running h : high level l : low level notes: 1. differential cl ock pairs (y [0:9], y[0:9] ) can be set to high impedance state via the i 2 c register.
HD74CDCV851 rev.6, dec. 2002, page 3 of 16 pin arrangement 1 2 3 4 5 6 7 8 9 10 gnd y0 y0 vdd y1 y1 gnd gnd y2 vdd sclk clkin nc vddi avdd agnd gnd y3 y3 vdd y4 y4 gnd y2 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 gnd y9 y9 y8 y8 nc nc fbout sdata y7 y7 gnd gnd gnd y6 y6 y5 gnd y5 vdd vdd fbin vdd vdd (top view)
HD74CDCV851 rev.6, dec. 2002, page 4 of 16 pin functions pin name no. type description agnd 17 ground analog ground. agnd provid es the ground reference for the analog circuitry. avdd 16 power analog power supply. avdd provides the power reference for the analog circuitry. in addition, avdd can be used to bypass the pll for test purposes. when avdd is strapped to ground, pll is bypassed and clk is buffered directly to the device outputs. clkin 13 input clock input. clkin provides the clock signal to be distributed by the HD74CDCV851 clock buffer. clk is used to provide the reference signal to the integrated pll that generates the clock output signals. clk must have a fixed frequency and fixed phase for the pll to obtain phase lock. once the circuit is powered up and a valid clk signal is applied, a stabilization time is required for the pll to phase lock the feedback signal to its reference signal. fbin 35 input feedback input. fbin provides the feedback signal to the internal pll. fbin must be hard-wired to fbout to complete the pll. the integrated pll sy nchronizes clkin and fbin so that there is nominally zero phase error between clkin and fbin. fbout 33 output feedback output. fbout is dedicated for external feedback. it switches at the same frequency as clk. when externally wired to fbin, fbout completes the feedback loop of the pll. sdata 37 input data input for i 2 c logic. integrated resistor pulls up this pin. (120 k ? typ) sclk 12 input clock input for i 2 c logic. integrated resistor pulls up this pin. (120 k ? typ) gnd 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 ground ground vddi 15 power power supply for i 2 c logic. vdd 4, 11, 21, 28, 34, 38, 45 power power supply y 3, 5, 10, 20, 22, 27, 29, 39, 44, 46 output clock outputs. (+clock) t hese outputs provide low-skew copies of clk. y 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 output bar clock outputs. (?clock) these outputs provide low-skew copies of clk. nc 14, 32, 36 nc don?t connect any vdd or gnd.
HD74CDCV851 rev.6, dec. 2002, page 5 of 16 block diagram i 2 c lo g i c s dat a sc l k y0 y0 pll 1 /2 ( 2x fclk ) fbin c lki n y9 fbout y9 vddi
HD74CDCV851 rev.6, dec. 2002, page 6 of 16 i 2 c controlled register bit map the i 2 c controlled register bytes are used to control the output clock pairs. the output pairs are enabled after power-up. during normal operation, the clock pairs can be disable (high impedance) or enable (running) by writing the corresponding bit in i 2 c control bytes in the following table. byte0 reserved register bit description contents default 7 (reserved bit) 1 6 (reserved bit) 1 5 (reserved bit) 1 4 (reserved bit) 1 3 (reserved bit) 1 2 (reserved bit) 1 1 (reserved bit) 1 0 (reserved bit) 1 byte1 reserved register bit description contents default 7 (reserved bit) 1 6 (reserved bit) 1 5 (reserved bit) 1 4 (reserved bit) 1 3 (reserved bit) 1 2 (reserved bit) 1 1 (reserved bit) 1 0 (reserved bit) 1
HD74CDCV851 rev.6, dec. 2002, page 7 of 16 i 2 c controlled register bit map (cont.) byte2 reserved register bit description contents default 7 (reserved bit) 1 6 (reserved bit) 1 5 (reserved bit) 1 4 (reserved bit) 1 3 (reserved bit) 1 2 (reserved bit) 1 1 (reserved bit) 1 0 (reserved bit) 1 byte3 reserved register bit description contents default 7 (reserved bit) 1 6 (reserved bit) 1 5 (reserved bit) 1 4 (reserved bit) 1 3 (reserved bit) 1 2 (reserved bit) 1 1 (reserved bit) 1 0 (reserved bit) 1
HD74CDCV851 rev.6, dec. 2002, page 8 of 16 i 2 c controlled register bit map (cont.) byte4 reserved register bit description contents default 7 (reserved bit) 1 6 (reserved bit) 1 5 (reserved bit) 1 4 (reserved bit) 1 3 (reserved bit) 1 2 (reserved bit) 1 1 (reserved bit) 1 0 (reserved bit) 1 byte5 ddr clock out control register bit description contents default 7 clock enable control bit (y0) 1 6 clock enable control bit (y1) 1 5 clock enable control bit (y2) 1 4 clock enable control bit (y3) 1 3 clock enable control bit (y4) 1 2 clock enable control bit (y9) 0 = yn differential clock out pair will be high impedance (output disable) 1 = yn differential clock out pair will be enabled all outputs are enabled at power-on. 1 1 (reserved bit) 1 0 (reserved bit) 1
HD74CDCV851 rev.6, dec. 2002, page 9 of 16 i 2 c controlled register bit map (cont.) byte6 ddr clock out control register bit description contents default 7 (reserved bit) 0 6 (reserved bit) 0 5 (reserved bit) 0 4 clock enable control bit (y8) 1 3 clock enable control bit (y7) 1 2 clock enable control bit (y6) 1 1 clock enable control bit (y5) 0 = yn differential clock out pair will be high impedance (output disable) 1 = yn differential clock out pair will be enabled all outputs are enabled at power-on. 1 0 (reserved bit) 1
HD74CDCV851 rev.6, dec. 2002, page 10 of 16 absolute maximum ratings item symbol ratings unit conditions supply voltage vdd ?0.5 to 3.6 v v is ?0.5 to 5.5 v sclk, sdata v ic ?0.5 to 3.6 v clkin input voltage v i ?0.5 to vdd+0.5 v output voltage *1 v o ?0.5 to vdd+0.5 v input clamp current i ik ?50 ma v i < 0 output clamp current i ok ?50 ma v o < 0 continuous output current i o 50 ma v o = 0 to vdd maximum power dissipation at ta = 55c (in still air) 0.7 w storage temperature t stg ?65 to +150 c notes: stresses beyond those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ratings only, an d functional operation of the device at these or any other conditions beyond those indicated un der ?recommended operating conditions? is not implied. exposure to absolute maximum rated co nditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions item symbol min typ max unit conditions supply voltage avdd 2.3 2.5 2.7 v output supply voltage vdd 2.3 2.5 2.7 v i 2 c supply voltage vddi 2.3 3.3 3.6 v dc input signal voltage ?0.3 ? vdd+0.3 v all pins high level input voltage v ih 0.7 vddi ? ? v sclk, sdata low level input voltage v il ?0.3 ? 0.3 vddi v sclk, sdata v ihclk 1.7 ? 3.6 clkin high level input voltage v ihfb 1.7 ? vdd+0.3 v fbin low level input voltage v il ?0.3 ? 0.7 v clkin, fbin output differential cross point voltage v ox 0.5 vdd ?0.2 ?0.5 vdd +0.2 v output current i oh ? ? ?12 ma i ol ??12 input clock slew rate sr 1 ? ? v/ns operating temperature t a 0?70c note: unused inputs must be held high or low to prevent them from floating.
HD74CDCV851 rev.6, dec. 2002, page 11 of 16 electrical characteristics item symbol min typ max unit test conditions input clamp voltage (all inputs) v ik ? ? ?1.2 v i i = ?18 ma, vdd = 2.3 v v oh vdd?0.2 ??vi oh = ?100 a, vdd = 2.3 to 2.7 v 1.7 ? vdd i oh = ?12 ma, vdd = 2.3 v v ol ??0.2 i ol = 100 a, vdd = 2.3 to 2.7 v output voltage ??0.6 i ol = 12 ma, vdd = 2.3 v input current i i ?10 ? 10 a v i = 0 v or 2.7 v, vdd = 2.7 v, clkin, fbin analog supply current ai cc ? ? 12 ma vdd = avdd = 2.7 v, 170 mhz *1 dynamic supply current di cc ? 250 300 ma vdd = avdd = 2.7 v, 170 mhz all yn, yn , = open *1 input capacitance c i 2.5 ? 3.5 pf clkin and fbin *1 delta input capacitance c di ?0.25 ? 0.25 pf *1 notes: 1. target of design, not 100% tested in production.
HD74CDCV851 rev.6, dec. 2002, page 12 of 16 switching characteristics ta = 25 c, vdd = avdd = 2.5v item symbol min typ max unit test conditions period jitter t per ?|75|?ps * 7, 8 half period jitter t hper ? |100| ? ps * 8 cycle to cycle jitter t cc ?|75|?ps static phase offset t spe ? |120| ? ps * 4, 5 output clock skew t sk ? 100 ? ps operating clock frequency f clk(o) 60 ? 170 mhz * 1, 2 application clock frequency f clk(a) 95 133 170 mhz * 1, 3 slew rate 1.0 ? 2.0 v/ns 20% to 80% stabilization time ? ? 0.1 ms * 6 notes: target of design, not 100% tested in production. 1. the pll must be able to handle spread spec trum induced skew. (the specification for this frequency modulation can be found in the latest intel pc100 registered dimm specification) 2. operating clock frequency indicates a range ov er which the pll must be able to lock, but in which it is not required to meet the other timi ng parameters. (used for low speed system debug.) 3. application clock frequency indicates a rang e over which the pll must meet all timing parameters. 4. assumes equal wire length and loading on the clock output and feedback path. 5. static phase offset does not include jitter. 6. stabilization time is the time required for the integrated pll circuit to obtain phase lock of it?s feedback signal to it?s reference signal after power on. 7. period jitter defines the largest variation in clock period, around a nominal clock period. 8. period jitter and half period jitter are separate s pecifications that must be met independently of each other.
HD74CDCV851 rev.6, dec. 2002, page 13 of 16 dc electrical characteristics / i 2 c serial input port ta = 0 to 70c, vddi = 3.3 v0.3 v or vddi = 2.5 v0.2 v item symbol min typ max unit test conditions input low voltage v il ??0.8v input high voltage v ih 2.0 ? ? v input current i i ?50 ? 10 av i = 0 v or 3.6 v, vdd = 3.6 v input capacitance c i ? ? 10 pf sdata & sclk note: target of design, not 100% tested in production. ac electrical characteristics / i 2 c serial input port item symbol min typ max unit test conditions notes sclk frequency f sclk ? ? 100 khz normal mode start hold time t sthd 4.0 ? ? s sclk low time t low 4.7 ? ? s sclk high time t high 4.0 ? ? s data setup time t dsu 250 ? ? ns data hold time t dhd 0 ??ns rise time t r ? ? 1000 ns sdata & sclk 0.8 v to 2.0 v fall time t f ? ? 300 ns sdata & sclk 2.0 v to 0.8 v stop setup time t stsu 4.0 ? ? s bus free time between stop & start condition t spf 4.7 ? ? s note: target of design, not 100% tested in production.
HD74CDCV851 rev.6, dec. 2002, page 14 of 16 r = 120 ? zo = 60 ? yn note: 1. sdram cin 3.5 pf 4 zo = 60 ? yn t c = 14 pf *1 *1 c = 14 pf figure 1 clock outputs test circuit yn yn tcycle n t = (tcycle n) - (tcycle n+1) cc tcycle n+1 figure 2 cycle to cycle jitter yx yx yy yy tsk figure 3 output clock skew (differential clock output)
HD74CDCV851 rev.6, dec. 2002, page 15 of 16 package dimensions 0.13 m 0.15 7.50 0.3 124 25 48 15.85 0.3 0.635 0.78 max 0.10 min 2.65 max 10.40 0.4 0.60 0.2 1.45 0.25 0.1 0.15 0.05 0 - 10 unit : mm
HD74CDCV851 rev.6, dec. 2002, page 16 of 16 disclaimer 1. hitachi neither warrants nor grants licenses of any rights of hitachi?s or any third party?s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party?s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifi cations before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi?s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunc tion may directly threaten human life or cause risk of bodily injury, such as aerosp ace, aeronautics, nuclear power, co mbustion control, transportation, traffic, safety equipment or me dical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage rang e, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. ev en within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor de vices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to op eration of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi?s sales office fo r any questions regarding this document or hitachi semiconductor products. sales offices hitachi, ltd. semiconductor & integrated circuits nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: (03) 3270-2111 fax: (03) 3270-5109 copyright ? hitachi, ltd., 2002. all rights reserved. printed in japan. hitachi asia ltd. hitachi tower 16 collyer quay #20-00 singapore 049318 tel : <65>-6538-6533/6538-8577 fax : <65>-6538-6933/6538-3877 url : http://semiconductor.hitachi.com.sg url http://www.hitachisemiconductor.com/ hitachi asia ltd. (taipei branch office) 4/f, no. 167, tun hwa north road hung-kuo building taipei (105), taiwan tel : <886>-(2)-2718-3666 fax : <886>-(2)-2718-8180 telex : 23222 has-tp url : http://semiconductor.hitachi.com.tw hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel : <852>-2735-9218 fax : <852>-2730-0281 url : http://semiconductor.hitachi.com.hk hitachi europe gmbh electronic components group dornacher str 3 d-85622 feldkirchen postfach 201, d-85619 feldkirchen germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi europe ltd. electronic components group whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi semiconductor (america) inc. 179 east tasman drive san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: colophon 7.0

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